// SPDX-License-Identifier: MIT
/*
 * Copyright © 2019 Intel Corporation
 */

#include "i915_drv.h"

#include "intel_breadcrumbs.h"
#include "intel_context.h"
#include "intel_engine.h"
#include "intel_engine_heartbeat.h"
#include "intel_engine_pm.h"
#include "intel_gt.h"
#include "intel_gt_ccs_mode.h"
#include "intel_gt_pm.h"
#include "intel_rc6.h"
#include "intel_ring.h"
#include "shmem_utils.h"
#include "intel_gt_regs.h"

static int __engine_unpark(struct intel_wakeref *wf)
{
	struct intel_engine_cs *engine =
		container_of(wf, typeof(*engine), wakeref);

	ENGINE_TRACE(engine, "\n");

	GEM_BUG_ON(engine->i915->quiesce_gpu);

	engine->wakeref_track = intel_gt_pm_get(engine->gt);

	if (engine->unpark)
		engine->unpark(engine);

	intel_breadcrumbs_unpark(engine->breadcrumbs);
	intel_engine_unpark_heartbeat(engine);
	return 0;
}

#if IS_ENABLED(CONFIG_LOCKDEP)

static unsigned long __timeline_mark_lock(struct intel_context *ce)
{
	unsigned long flags;

	local_irq_save(flags);
	mutex_acquire(&ce->timeline->mutex.dep_map, 2, 0, _THIS_IP_);

	return flags;
}

static void __timeline_mark_unlock(struct intel_context *ce,
				   unsigned long flags)
{
#ifdef BPM_LOCKING_NESTED_ARG_NOT_PRESENT
	mutex_release(&ce->timeline->mutex.dep_map, 0, _THIS_IP_);
#else
	mutex_release(&ce->timeline->mutex.dep_map, _THIS_IP_);
#endif
	local_irq_restore(flags);
}

#else

static unsigned long __timeline_mark_lock(struct intel_context *ce)
{
	return 0;
}

static void __timeline_mark_unlock(struct intel_context *ce,
				   unsigned long flags)
{
}

#endif /* !IS_ENABLED(CONFIG_LOCKDEP) */

static void duration(struct dma_fence *fence, struct dma_fence_cb *cb)
{
	struct i915_request *rq = to_request(fence);

	ewma__engine_latency_add(&rq->engine->latency,
				 ktime_us_delta(rq->fence.timestamp,
						rq->duration.emitted));
}

static void
__queue_and_release_pm(struct i915_request *rq,
		       struct intel_timeline *tl,
		       struct intel_engine_cs *engine)
{
	struct intel_gt_timelines *timelines = &engine->gt->timelines;

	ENGINE_TRACE(engine, "parking\n");

	GEM_BUG_ON(rq->context->active_count != 1);
	__intel_gt_pm_get(engine->gt);
	rq->context->wakeref = intel_wakeref_track(&engine->gt->wakeref);

	/*
	 * We have to serialise all potential retirement paths with our
	 * submission, as we don't want to underflow either the
	 * engine->wakeref.counter or our timeline->active_count.
	 *
	 * Equally, we cannot allow a new submission to start until
	 * after we finish queueing, nor could we allow that submitter
	 * to retire us before we are ready!
	 */
	spin_lock(&timelines->lock);

	/* Let intel_gt_retire_requests() retire us (acquired under lock) */
	if (!atomic_fetch_inc(&tl->active_count))
		list_add_tail(&tl->link, &timelines->active_list);

	/* Hand the request over to HW and so engine_retire() */
	__i915_request_queue_bh(rq);

	/* Let new submissions commence (and maybe retire this timeline) */
	__intel_wakeref_defer_park(&engine->wakeref);

	spin_unlock(&timelines->lock);
}

static bool switch_to_kernel_context(struct intel_engine_cs *engine)
{
	struct intel_context *ce = engine->kernel_context;
	struct i915_request *rq;
	unsigned long flags;
	bool result = true;

	/*
	 * This is execlist specific behaviour intended to ensure the GPU is
	 * idle by switching to a known 'safe' context. With GuC submission, the
	 * same idle guarantee is achieved by other means (disabling
	 * scheduling). Further, switching to a 'safe' context has no effect
	 * with GuC submission as the scheduler can just switch back again.
	 *
	 * FIXME: Move this backend scheduler specific behaviour into the
	 * scheduler backend.
	 */
	if (intel_engine_uses_guc(engine))
		return true;

	/* GPU is pointing to the void, as good as in the kernel context. */
	if (intel_gt_is_wedged(engine->gt))
		return true;

	GEM_BUG_ON(!intel_context_is_barrier(ce));

	/* Already inside the kernel context, safe to power down. */
	if (engine->wakeref_serial == engine->serial)
		return true;

	/*
	 * Note, we do this without taking the timeline->mutex. We cannot
	 * as we may be called while retiring the kernel context and so
	 * already underneath the timeline->mutex. Instead we rely on the
	 * exclusive property of the __engine_park that prevents anyone
	 * else from creating a request on this engine. This also requires
	 * that the ring is empty and we avoid any waits while constructing
	 * the context, as they assume protection by the timeline->mutex.
	 * This should hold true as we can only park the engine after
	 * retiring the last request, thus all rings should be empty and
	 * all timelines idle.
	 *
	 * For unlocking, there are 2 other parties and the GPU who have a
	 * stake here.
	 *
	 * A new gpu user will be waiting on the engine-pm to start their
	 * engine_unpark. New waiters are predicated on engine->wakeref.count
	 * and so intel_wakeref_defer_park() acts like a mutex_unlock of the
	 * engine->wakeref.
	 *
	 * The other party is intel_gt_retire_requests(), which is walking the
	 * list of active timelines looking for completions. Meanwhile as soon
	 * as we call __i915_request_queue(), the GPU may complete our request.
	 * Ergo, if we put ourselves on the timelines.active_list
	 * (se intel_timeline_enter()) before we increment the
	 * engine->wakeref.count, we may see the request completion and retire
	 * it causing an underflow of the engine->wakeref.
	 */
	flags = __timeline_mark_lock(ce);
	GEM_BUG_ON(atomic_read(&ce->timeline->active_count) < 0);

	rq = __i915_request_create(ce, GFP_NOWAIT);
	if (IS_ERR(rq))
		/* Context switch failed, hope for the best! Maybe reset? */
		goto out_unlock;

	/* Check again on the next retirement. */
	engine->wakeref_serial = engine->serial + 1;
	i915_request_add_active_barriers(rq);

	/* Install ourselves as a preemption barrier */
	rq->sched.attr.priority = I915_PRIORITY_BARRIER;

	GEM_BUG_ON(i915_active_fence_isset(&ce->timeline->last_request));
	__i915_request_commit(rq); /* engine should be idle! */

	/*
	 * Use an interrupt for precise measurement of duration,
	 * otherwise we rely on someone else retiring all the requests
	 * which may delay the signaling (i.e. we will likely wait
	 * until the background request retirement running every
	 * second or two).
	 */
	BUILD_BUG_ON(sizeof(rq->duration) > sizeof(rq->submitq));
	dma_fence_add_callback(&rq->fence, &rq->duration.cb, duration);
	rq->duration.emitted = ktime_get();

	/* Expose ourselves to the world */
	__queue_and_release_pm(rq, ce->timeline, engine);

	result = false;
out_unlock:
	__timeline_mark_unlock(ce, flags);
	return result;
}

static void call_idle_barriers(struct intel_engine_cs *engine)
{
	struct list_head *node, *next;

	list_for_each_safe(node, next, &engine->barrier_tasks) {
		struct dma_fence_cb *cb = container_of(node, typeof(*cb), node);

		cb->func(IDLE_BARRIER, cb);
	}
	INIT_LIST_HEAD(&engine->barrier_tasks);
}

static int __engine_park(struct intel_wakeref *wf)
{
	struct intel_engine_cs *engine =
		container_of(wf, typeof(*engine), wakeref);

	engine->saturated = 0;

	/*
	 * If one and only one request is completed between pm events,
	 * we know that we are inside the kernel context and it is
	 * safe to power down. (We are paranoid in case that runtime
	 * suspend causes corruption to the active context image, and
	 * want to avoid that impacting userspace.)
	 */
	if (!switch_to_kernel_context(engine))
		return -EBUSY;

	ENGINE_TRACE(engine, "parked\n");

	call_idle_barriers(engine); /* cleanup after wedging */

	intel_engine_park_heartbeat(engine);
	intel_breadcrumbs_park(engine->breadcrumbs);

	if (engine->park)
		engine->park(engine);

	intel_gt_park_ccs_mode(engine->gt, engine);

	/* While gt calls i915_vma_parked(), we have to break the lock cycle */
	intel_gt_pm_put_async(engine->gt, engine->wakeref_track);
	return 0;
}

static const struct intel_wakeref_ops wf_ops = {
	.get = __engine_unpark,
	.put = __engine_park,
};

void intel_engine_init__pm(struct intel_engine_cs *engine)
{
	struct drm_i915_private *i915 = engine->i915;
	struct intel_runtime_pm *rpm = engine->uncore->rpm;

	intel_wakeref_init(&engine->wakeref, rpm, &wf_ops, engine->name);
	intel_engine_init_heartbeat(engine);

	if (IS_METEORLAKE(i915) && engine->id == GSC0 && !IS_SRIOV_VF(i915)) {
		/* FIXME: Enable GSC CS Idle messaging */
		intel_uncore_write(engine->gt->uncore,
				   RC_PSMI_CTRL_GSCCS,
				   _MASKED_BIT_DISABLE(IDLE_MSG_DISABLE));
		drm_dbg(&i915->drm,
			"Set GSC CS Idle Reg to: 0x%x",
			intel_uncore_read(engine->gt->uncore, RC_PSMI_CTRL_GSCCS));
	}

}

struct i915_request *
intel_engine_create_kernel_request(struct intel_engine_cs *engine)
{
	struct i915_request *rq;

	/*
	 * The engine->kernel_context is special as it is used inside
	 * the engine-pm barrier (see __engine_park()), circumventing
	 * the usual mutexes and relying on the engine-pm barrier
	 * instead. So whenever we use the engine->kernel_context
	 * outside of the barrier, we must manually handle the
	 * engine wakeref to serialise with the use inside.
	 */
	intel_engine_pm_get(engine);

	rq = i915_request_create(engine->kernel_context);
	if (!IS_ERR(rq)) {
		engine->wakeref_serial = engine->serial + 1;
		i915_request_add_active_barriers(rq);
	}

	intel_engine_pm_put(engine);

	return rq;
}

#if IS_ENABLED(CPTCFG_DRM_I915_SELFTEST)
#include "selftest_engine_pm.c"
#endif
